Makefile syntax

file myMakefile:
  # This is a comment
  # myprogram is built from file1.c file2.c and headerfile file.h
  
  # set compile variables for tools and environment
  # use gnu compiler
  CC = gcc
  # use full warnings  
  CFLAGS = -Wall
  OBJS = file1.o file2.o
  HEADERS = file.h

  # let make now that objs depend on headers. make knows what to do then.
  $(HEADERS): $(OBJS)
  # the space before $(CC) MUST BE A TAB!!!
  myprogram: $(OBJS)
      $(CC) -o myprogram $(OBJS)